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Version Shell : 1.0 (Release candidate)

Author : FierzaXploit/Mr.MF33

PATH : /proc/self/root/opt/alt/python37/share/doc/alt-python37-pyparsing-doc/examples/verilog/

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//
// Demonstrate how to display strings for a particular signal.
// This allows you to see a text string for a bus, which at times, might
// help out in debugging.  This is not intended for synthesis, of course.
// Keep these funny "string" signals seperate so we can disable them
// at synthesis time and so they never impact the circuit.
//
//
module test;

// Declare a register with enough bits for the ASCII string.
// synopsys translate_off
reg [9*8-1:0] string_signal; // **** FOR TESTING
// synopsys translate_on

// Here's the *real* circuit signal
reg [3:0] shift_register;

reg clk, reset;

// Here's the real circuit
always @(posedge clk)
   if (reset) shift_register <= 4'b0001;
   else       shift_register <= {shift_register[2:0], shift_register[3]};

// Now we assign to our string signal based on the real signal.
// Disable this code when synthesizing.
//   
// synopsys translate_off
always @(shift_register)
   case (shift_register)
      4'b0001: string_signal <= "BIT  ZERO";
      4'b0010: string_signal <= "BIT   ONE";
      4'b0100: string_signal <= "BIT   TWO";
      4'b1000: string_signal <= "BIT THREE";
      default: string_signal <= "?????????";                  
   endcase
// synopsys translate_on

initial begin
   clk =  0;
   forever begin
      #10 clk = ~clk;
   end
end

initial begin
   reset = 0;
   #2 reset = 1;  
   #13 reset = 0;
   #200;
   $finish;
end

// Generate VCD file for viewing.
//
// Once we are in the Waveform Viewer, just set the format of 'string_signal'
// to ASCII!
//
initial begin
   $dumpfile ("test_string_signal.vcd");
   $dumpvars (0,test);   
end

endmodule

Type	Name	options
	hasCompilerDirectives
	new
	new2
	new3
	parseOutput
	Ctr3sr.v
	INIT
	RANDOM_GATE
	RANDOM_INTERCONNECT
	SEED
	TestCtr3sr.v
	addacc.v
	addacc1_dro.v
	addacc1_t1ff.v
	addacc_conf.v
	addacc_dro.v
	addacc_t1ff.v
	allParseOutput.zip
	and.v
	and_gate.v
	conf.v
	core_test.v
	count2bit.v
	count_all_prims_test.v
	count_loads_test.v
	dds.v
	diff_udp.v
	display_all_nets_test.v
	div16.v
	dro.v
	dro1_cell.v
	dro_cell.v
	dump_and_fill_mem_test.v
	exprinfo_test.v
	fetch_values_test.v
	ff.v
	ff_test.v
	fifo.v
	find_driver.tcl.gz
	framer.v
	func_72bit_test.v
	gen.v
	gencrc.v
	gzip.exe
	hadd.v
	hasCompilerDirectives
	hello_test.v
	in_port.v
	inv.v
	inv_cell.v
	invoke_commands_test.v
	invoke_options_test.v
	jtl2.v
	jutzi
	list_cells_test.v
	list_nets_test.v
	list_parameters_test.v
	list_path_delays_test.v
	list_pathout_ports_test.v
	list_prim_delays_test.v
	load_in.v
	load_out.v
	mem_arb.v
	mipd_delays_test.v
	mult16.v
	multi21_udp.v
	my_monitor1_test.v
	my_monitor2_test.v
	my_monitor_test.v
	my_strobe_test.v
	myram64x16.v
	nco.v
	ndro.v
	new
	new2
	new3
	nodeinfo_test.v
	onehot.v
	or.v
	out_port.v
	parseOutput
	pic.v
	pipe1.v
	pipe2.v
	pl.v
	pli_handbook_examples_pc.zip
	port_info_test.v
	pow_test.v
	primitives.v
	propagatep_test.v
	psr1.v
	psr1_conf.v
	psr1_dro.v
	psr1_split.v
	psr2.v
	psr2_and.v
	psr2_split.v
	read_4state_value_test.v
	read_attribute_test.v
	read_delays_test.v
	read_stimulus_short_test.v
	read_stimulus_test.v
	read_strengthval_test.v
	read_test_vector_test.v
	read_timeval_test.v
	read_vector_test.v
	read_vecval_test.v
	realpow_test.v
	rf.v
	sci_alu_comb_calltf_shell.v
	sci_alu_comb_calltf_test.v
	sci_alu_comb_misctf_shell.v
	sci_alu_comb_misctf_test.v
	sci_alu_combinational_shell.v
	sci_alu_combinational_test.v
	sci_alu_latched_shell.v
	sci_alu_latched_test.v
	sci_alu_sequential_shell.v
	sci_alu_sequential_test.v
	sci_alu_synchronized_shell.v
	sci_alu_synchronized_test.v
	sci_alu_with_delays_shell.v
	sci_alu_with_delays_test.v
	set_mipd_delays_test.v
	show_all_nets_test.v
	show_all_signals1_test.v
	show_all_signals2_test.v
	show_all_signals3_test.v
	show_all_signals_1_test.v
	show_all_signals_2_test.v
	show_all_signals_3_test.v
	show_value_test.v
	sig_gen.v
	simple_core.v
	splitter.v
	sqrt32.v
	sqrt8m.v
	sr_nv_ctf.v
	srcnt.v
	string.v
	t1ff.v
	testcase.v
	testcase2.v
	testcase3.v
	testcase4.v
	testcase5.v
	tff.v
	timescale_info_test.v
	usb.v
	use_workarea_test.v
	utmi_if.v
	vpi_utilities_test.v
	wb.v
	wpulse.v
	xor.v
	zzzexample.v